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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES6210/D Rev 1, 03/2002
Low Voltage 2.5/3.3V Differential ECL/PECL/HSTL Fanout Buffer
The Motorola MC100ES6210 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6210 supports various applications that require to distribute precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low clock skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. Features: * Dual 1:5 differential clock distribution
MC100ES6210
LOW VOLTAGE DUAL 1:5 DIFFERENTIAL PECL/ECL/HSTL CLOCK FANOUT BUFFER
Pin and function compatible to the MC100EP210 Functional Description The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6210 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.
* * * * * * * * * *
30 ps maximum device skew Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Supports DC to 3GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3V, -3.3V, 2.5V or -2.5V supply Standard 32 lead LQFP package Industrial temperature range
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
(c) Motorola, Inc. 2002
MC100ES6210
QA3 QA3 AQ4 QA4 QB0 QB0 QB1 18 QB1 17 16 15 14 13 VCC QB2 QB2 QB3 QB3 QB4 QB4 VCC 12 11 10 9 1 2 3 4 5 6 7 8 VEE
QA0 QA0 VCC QA1 QA1 QA2 QA2 QA3 QA3 QA4 QA4 QB0 QB0 VCC QB1 QB1 QB2 QB2 QB3 QB3 QB4 QB4 VBB
24 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28
23
22
21
20
19
CLKA CLKA
MC100ES6210
29 30 31 32
CLKB CLKB
VCC
N.C.
CLKA
CLKA
CLKB
Figure 1.MC100ES6210 Logic Diagram Table 1. Pin configuration
Pin CLKA, CLKA CLKB, CLKB QA[0-4], QA[0-4] QB[0-4], QB[0-4] VEEa VCC VBB I/O Input Input Output Output Supply Supply Output DC Type ECL/PECL ECL/PECL ECL/PECL ECL/PECL
Figure 2.32-Lead Package Pinout (Top View)
Function Differential reference clock signal input (fanout buffer A) Differential reference clock signal input (fanout buffer B) Differential clock outputs (fanout buffer A) Differential clock outputs (fanout buffer B) Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Reference voltage output for single ended ECL or PECL operation
a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V . In both modes, the input and output levels are referenced to the most positive supply (VCC).
MOTOROLA
2
CLKB
VBB
TIMING SOLUTIONS
MC100ES6210
Table 2. ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 3. General Specifications
Symbol VTT MM HBM CDM LU CIN JA Thermal resistance junction to ambient JESD 51-3, single layer tes board Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up immunity 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 200 2000 Min Typ VCC - 2a Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
JESD 51-6, 2S2P multilayer test board
JC TJ
Thermal resistance junction to case Operating junction temperatureb (continuous operation) MTBF = 9.1 years
110
C
a. Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase b. Operating junction temperature impacts device life time. Maximum continues operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
TIMING SOLUTIONS
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MOTOROLA
MC100ES6210
Table 4. PECL DC Characteristics (VCC = 2.5V 5% or VCC = 3.3V 5%, VEE = GND, TJ = 0C to +110C)
Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLKA, CLKA, CLKB, CLKB (PECL differential signals) VPP VCMR IIN Differential input voltagea Differential cross point voltageb Input Currenta 0.1 1.0 1.3 VCC - 0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH IOH = -30 mAc IOL = -5 mAc
PECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4) VOH VOL Output High Voltage Output Low Voltage VCC = 3.3V5% VCC = 2.5V5% VCC-1.2 VCC-1.9 VCC-1.9 VCC-1.005 VCC-1.705 VCC-1.705 VCC-0.7 VCC-1.5 VCC-1.3 V V
Supply current and VBB IEE Maximum Quiescent Supply Current without output termination current 60 100 mA VEE pin
VBB Output reference voltage VCC-1.38 VCC-1.26 VCC-1.14 V IBB = 0.2 mA a. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality b. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. c. Equivalent to a termination of 50W to VTT.
Table 5. ECL DC Characteristics (VEE = -2.5V 5% or VEE = -3.3V 5%, VCC = GND, TJ = 0C to +110C)
Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP VCMR IIN Differential input voltagea Differential cross point voltageb Input Currenta 0.1 VEE + 1.0 1.3 -0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH IOH = -30 mAc IOL = -5 mAc
ECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4) VOH VOL Output High Voltage Output Low Voltage VCC = 3.3V5% VCC = 2.5V5% -1.2 -1.9 -1.9 -1.005 -1.705 -1.705 -0.7 -1.5 -1.3 V V
Supply current and VBB IEE Maximum Quiescent Supply Current without output termination current 60 100 mA VEE pin
VBB Output reference voltage -1.38 -1.26 -1.14 V IBB = 0.2 mA a. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality b. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. c. Equivalent to a termination of 50W to VTT.
MOTOROLA
4
TIMING SOLUTIONS
MC100ES6210
Table 6. AC Characteristics (ECL: VEE = -3.3V 5% or VEE = -2.5V 5%, VCC = GND) or (PECL: VCC = 3.3V 5% or VCC = 2.5V 5%, VEE = GND, TJ = 0C to +110C)a b
Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals) VPP VCMR Differential input voltagec (peak-to-peak) Differential input crosspoint voltaged PECL ECL ECL clock outputs (Q0-9, Q0-9) fCLK tPD VO(P-P) Input Frequency Propagation Delay CLKA to QAx or CLKB to QBx Differential output voltage (peak-to-peak) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz Output-to-output skew (per bank) Output-to-output skew (part-to-part) Output cycle-to-cycle jitter Output pulse skewe Output Duty Cycle Output Rise/Fall Time fREF < 0.1 GHz fREF < 1.0 GHz 49.5 45.0 30 50 50 0 175 0.45 0.35 0.20 260 0.70 0.55 0.35 13 30 175 TBD 50 50.5 55.0 250 ps % % ps DCREF = 50% DCREF = 50% 20% to 80% 3000 350 MHz ps V V V ps ps Differential Differential Differential Differential 1.2 VEE+1.2 VCC - 0.3 -0.3V V V 0.3 0.3 1.3 V
tsk(O) tsk(PP) tJIT(CC) tSK(P) DCQ tr, tf
a. AC characteristics are design targets and pending characterization. b. AC characteristics apply for parallel output termination of 50 to VTT. c. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. d. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. e. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
Differential Pulse Generator Z = 50W
ZO = 50
ZO = 50
RT = 50 VTT
DUT MC100ES6210
RT = 50 VTT
Figure 3.MC100ES6210 AC test reference
TIMING SOLUTIONS
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MOTOROLA
MC100ES6210
NOTES
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TIMING SOLUTIONS
MC100ES6210
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
7
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
MC100ES6210
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E Motorola, Inc. 2002.
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MOTOROLA
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MC100ES6210/D TIMING SOLUTIONS

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